A High Performance Junctionless PTGVMOS with Native Tie for Deca-nanometer Regime

摘要：

In this study, we propose a new technology to fabricate pseudo tri-gate vertical (PTGV) MOSFETs without p-n junctions, named junctionless PTGVMOS (JPTGV). According to numerical analysis, the excellent electrical characteristics such as subthreshold swing (S.S.)～60mV/dec, IJIoff～1010, and low interface trap density are all achieved. The device without p-n junctions provides an easier way for JPTGV fabrication and it can be employed for use in deca-nanometer regime.

作者: Yu-Che Chang Jyi-Tsong Lin Yi-Chuen Eng Po-Hsieh Lin

作者单位: Department of Electrical Engineering, National Sun Yat-Sen University 70 Lien-Hai Rd. Kaohsiung 80424, Taiwan, R.O.C

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 1006-1008

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）