Control of Low-k/Cu Interconnect Nanotechnology Processes Integration of High Aspect Ratio Hard Mask Patterning
A hard mask mechanism and fabrication processes integration for the modification interconnect fabrication processes of low-k and copper interconnects is proposed. When scaling the critical dimensions into nanotechnology, the impact of layout and line edge becomes important. Implementation of Cu and low dielectric constant (low-k) materials in the manufacturing process requires a complete understanding of these process characteristics and the challenges that appear during the hard mask based dual damascene approach. Processes integration of Cu with low k dielectrics provided solution to reduce resistance variation of BEOL interconnections for nanotechnology node. To suppress problems in the hard mask approach of photolithography and optimal etching pattering processes, the balance of the processes integration should be quantitatively and instantaneously controlled to the optimum wafer fabrication technologies.
Chun-Jen Weng
Dept. of Technology Management, Leader University, Tainan, Taiwan, R.O.C
国际会议
上海
英文
1030-1032
2010-11-01（万方平台首次上网日期，不代表论文的发表时间）