Improvement of Electrical Characteristics on P+Source/Drain Ion Implantation by N2 Anneal for NAND Flash Memory
In this study, we investigated the electrical characteristics of p-channel transistor by changing the process sequence of P+ Source/Drain Ion Implantation (IIP) N2 annealing process in NAND Flash memory. For the case of changing the process sequence of N2 annealing, off-current of p-channel transistor was dropped sharply, and increase of the on current compared to the off current is not worse than the conventional N2 annealing scheme. It seems to be resulted from the suppression of source/drain ion implantation dopant diffusion. In summary, there is the same Ion-Ioff current characteristics with no off-current degradation. And as a result of P+ S/D IIP energy increase, breakdown voltage (BV) of p-channel transistor grows up and current characteristic has improved.
Young-suk Kim Hyun-mog Park Jong-ho Park
Flash Process Architecture Team, Memory Division, Samsung Electronics Co. Ltd , San ＃24 Nongseo-Dong, Giheung-Gu, Yongin-City, Gyeonggi-Do, Korea, 449-711 School of Information and Communication Engineering, Sungkyunkwan University, Suwon 440-746, Korea
国际会议
上海
英文
1169-1171
2010-11-01（万方平台首次上网日期，不代表论文的发表时间）