Pre-cycling with higher voltages for endurance improvement of silicon nanocrystal memory device

摘要：

Contradiction of threshold voltage shift window and endurance severely restricts the application of silicon nanocrystals (Si-NCs). Pre-cycling with higher program/erase (P/E) voltages greatly improves the endurance performance. Baked at 150 C, decreases of stored charges at programmed states have a similar trend, which proves the optimized method does not bring more traps than normal P/E cycling.

作者: Yong Wang Xiaonan Yang Qin Wang Zongliang Huo Manhong Zhang Bo Zhang Ming Liu

作者单位: Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China Grace Semiconductor Manufacturing Corporation, Shanghai, 201203, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 1265-1267

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）