III-V MOSFETs: Surface Passivation for Gate Stack,Source/Drain and Channel Strain Engineering, Self-Aligned Contact Metallization

摘要：

In this paper, we discuss the research and development of several key process modules for realizing high-mobility III-V n-MOSFETs. Interface passivation technologies were developed to realize high quality gate stacks on III-V. InGaAs MOSFETs with in situ doped lattice-mismatched source/drain (SID) stressors were demonstrated for reduction of S/D series resistance as well as channel strain engineering. InGaAs FETs with high-stress liner stressor were also realized. A CMOS-compatible salicide-like process was developed for self-aligned contact metallization. We also explore the integration of III-V on Si platform for potential device integration.

作者: Yee-Chia Yeo Hock-Chun Chin Xiao Gong Huaxin Guo Xingui Zhang

作者单位: Department of Electrical and Computer Engineering, National University of Singapore (NUS), Singapore 117576

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 1298-1301

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）