Study of High-gate-voltage Stress Using the Reverse Gated-diode Current Measurement in LDD n-type and p-type MOSFETs

摘要：

The reverse generation current under high gate voltage stress condition in LDD MOSFET has been studied. It is found that the generation current peak decreases as the stress time increases. It ascribes to the dominating oxide trapped electrons in n-MOSFET and trapped holes in p-MOSFET which reduce the effective drain bias so that lowering the maximal generation rate. The density of the effective trapped electrons in n-MOSFET and holes in p-MOSFET affecting the effective drain bias are calculated by using our model.

作者: Haifeng Chen Xiaohua Ma Huimin Du Lixin Guo Shiguang Shang Duan Xie

作者单位: School of Electronic Engineering, Xian University of Posts and Telecommunications, Xian 710121, Ch School of Microelectronics, Xidian University, Xian 710071, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 1630-1632

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）