FAST: A Framework of Accurate SER-Estimation at Transistor-Level for Logic Circuits

摘要：

With the development of VLSI technology, logic circuits are becoming more and more vulnerable to soft errors due to particle hits. In order to guide reliable logic circuit design, it is important to develop efficient tools for soft error rate estimation. In this paper, we present a framework FAST for accurate SER estimation in logic circuits. FAST models detailed behaviors of transient pulses in logic circuits at three phases, including SET generation, propagation and capture. Furthermore, FAST uses an accurate transistor-level linear model for estimating the possibility of transient pulse generation. Experimental results indicate that the proposed framework achieves good accuracy compared to the SPICE simulation, while it comes to a higher efficiency than electrical level simulation.

作者: Yan Sun Chao Song Yali Zhao Minxuan Zhang

作者单位: School of Computer,National University of Defense Technology, Changsha 410073, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 1707-1709

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）