A High Speed Low Power Interface for Inter-die Communication

摘要：

In this paper a current mode logic (CML) transceiver with ±250mV output swing is proposed. The CML transceiver is designed according to inter-die communication model analysis. The model includes both bonding wire and transmission line based on electromagnetic analysis. The CML transceiver is implemented in 1.8V 0.18μm technology. Simulation results show that the transceiver can reach 2.4Gbps data rate and consumes only 27mW.

作者: Siliang Hua Qi Wang Hao Yan Donghui Wang Chaohuan Hou

作者单位: Institute of Acoustics, Chinese Academy of Sciences, Beijing 100190, China Institute of Acoustics, Chinese Academy of Sciences, Beijing 100190, China Graduate University of Ch

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 1916-1918

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）