Modeling the Parasitic Bipolar Device in the 40nm PD SOI NMOS Device Considering the Floating Body Effect
This paper reports modeling the parasitic bipolar device in the 40nm PD SOI NMOS device considering the floating body effect. Using a unique extraction method, the function of the parasitic bipolar device during transient operations could be modeled. During the turn-on transient by imposing a step voltage from 0V to 2V at the gate, the case with a slower rise time shows a faster turn-on in the drain current due to a stronger function of the parasitic bipolar device from smaller displacement currents through the gate oxide, as reflected in the current gain, as verified by the experimentally measured results.
C. H. Chen J. B. Kuo D. Chen C. S. Yeh
Dept. of Electrical Eng, BL-528, National Taiwan University Roosevelt Rd. Sec 4, Taipei, Taiwan 106- UMC, Hsinchu, Taiwan 300
国际会议
上海
英文
1946-1948
2010-11-01(万方平台首次上网日期,不代表论文的发表时间)