Predictive Modeling of Capacitance and Resistance in Gate-all-around Cylindrical Nanowire MOSFETs for Parasitic Design Optimization
This paper presents a predictive electrostatic capacitance and resistance compact model of multiple gate MOSFET with cylindrical conducting channels, taking into account parasitic effects, quantum confinement and quasi-ballistic effects. The model incorporates the dependence of channel length, gate height and width, gate-to-contact spacing, nanowire size, multiple channels, as well as 1-D ultra-narrow source/drain extension (SDE) doping profile. The proposed non-iterative electrostatic model is successfully verified, and can be used to predict nanowire-based circuit performance. Based on the analytical model, we can further examine which parasitic components are affecting the delay. Results revealed that Qside. Cof, Rsd RQ are dominant factors and should be treated as a major design concern. Among all the parameters, Lsd Tg and Ndop are essentially important in parasitic design optimization. By selectively modifying these parameters, parasitic effect is evidently reduced.
Qiumin Xu Jibin Zou Jieyin Luo Runsheng Wang Ru Huang
Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics Peking University, Beijing 100871, China
国际会议
上海
英文
1958-1960
2010-11-01（万方平台首次上网日期，不代表论文的发表时间）