The implementation of the global scheduling strategy
Today the research on design for testability is becoming the research priority in the filed of SoC. However, the traditional research is limited in top level of SoC and it ignores the inference resulting from the scheduling strategy in IP-core level. In addition, the work on stage of SoC overly focuses on researching the minimum testing time of different WSC. It ignores the relationship between the WSC and testing time. So the traditional research doesnt play a significant role in design of SoC. In order to achieve the full use of testing resources, a bottomup global scheduling strategy based on WSC balancing scan chain is proposed in this paper. In this paper, we verify the algorithm and reusability of this strategy upon the ITC02 benchmark. Balancing test chain;driftwood algorithm;global scheduling strategy
Jinyi Zhang Jianhui Bu Wanlin Cai Jinshun Bi Chunhua Wang Mengxin Liu Haogang Cai Zhengsheng Han
Key Laboratory of Advanced Displays and system Application, Ministry of Education, Shanghai Universi Institute of Microelectronics of Chinese Academy and Sciences, Beijing 100029, China Microelectronic Research & Development Center, Shanghai University Key Laboratory of Special Fiber Optics and Optical Access Networks (Shanghai University), Ministry o Department of Mechanical Engineering, Columbia University, New York, NY 10027 USA
国际会议
上海
英文
1970-1972
2010-11-01（万方平台首次上网日期，不代表论文的发表时间）