Partial SOI Power LDMOS with a Variable Low-k Dielectric Buried Layer and a Buried P-layer

摘要：

A high voltage LDMOS on partial silicon-on-insulator (PSOI) with a variable low-k (relative permittivity) dielectric buried layer (VLKD) and a buried p-layer (BP) is proposed (VLKD BPSOI). In the vertical direction, the low k value enhances the electric field strength in the buried dielectric (E_1) and the Si window makes the substrate share the voltage drop, which leads to a high vertical breakdown voltage (BV). In the lateral direction, three interface field peaks are introduced by the BP, Si window and the VLKD, which modulates the fields in the top Si layer, VLKD layer and the substrate. A high BV is therefore obtained. Furthermore, the BP reduces the special onresistance (R_(on)) and the Si window alleviates the self-heating effect (SHE). Compared with the conventional PSOI, BV of VLKD BPSOI is enhanced by 43.5％ and R_(on) is decreased by 26.5％.

作者: Xiaorong Luo IEEE member Yuangang Wang Guoliang Yao Lianfei Lei Bo Zhang Zhaoji Li

作者单位: State key Laboratory of Electronic Thin Films and Integrated devices University of Electronic Science and Technology of China, Chengdu, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 2061-2063

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）