A Novel CMOS Inverter Composed of a Junctionless NMOSFET and a Gated N~--N-P~+Transistor for ULSI applications
In this paper, a novel non-classical CMOS inverter with simple process and high integration density is proposed, which is composed of a junctionless NMOSFET and a gated N~--N-P~+ transistor for driver and load, respectively. Also, the gated N~--N-P~+ transistor performance is also investigated. Based on the numerical simulations, we find out that the carrier mobility of the gated N~--N-P~+ transistor is enhanced significantly. Besides, the layout area of the novel CMOS inverter are reduced more than 46,1% because of its unique shared contacting for output node, when compared with the conventional layout area.
Kuan-Yu Lu Jyi-Tsong Lin Hsuan-Hsu Chen Yi-Chuen Eng
Dept. of Electrical Engineering, National Sun Yat-Sen University 70 Lien-Hai Rd., Kaohsiung 80424 Taiwan, R.O.C
国际会议
上海
英文
2064-2066
2010-11-01(万方平台首次上网日期,不代表论文的发表时间)