Image Filtering Using Partially and Dynamically Reconfiguration

摘要：

Modular based partially and dynamically reconfigurable (PDR) FPGA system is an ideal solution for run-time image processing system which needs to change the function of the processing unit dynamically. Here we present a new PDR image filter based on our self-developed FDP FPGA Device. In this system, the transition bus (TB) structure is proposed for physical separation of the static/dynamic blocks as required in PDR system. And we demo the system with an image filter aimed at filtering out mixnoise. The experiment results show that the proposed PDR system meets the requirement of the run-time image filter by its flexibility, fast reconfiguration speed, and saving of logic resource.

关键词： partially and dynamically reconfigurable system run-time image filter transition bus structure FDP FPGA Device

作者: Huaqiu Yang Fanjiong Zhang JinMei Lai Yan Wang

作者单位: ASIC & Systems State Key Lab, Fudan University 825 Zhangheng Rd., Shanghai, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 2067-2073

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）