Concurrent Error Detection in Systolic Array AB2 Multiplier using Linear Codes

摘要：

This investigation is based on a traditional AB2 systolic array multiplier 16 to derive a new CED AB2 multiplier using linear block codes. A novel linear encoding algebra is derived to realize parity-check functionality. It is based on the syndrome value, and is adopted to detect errors in the multiplication. Altera FPGA with stratix families to simulate our proposed CED multiplier. In the field GF(272), the space overhead of the proposed circuit is around 9.1％. The latency overhead only requires extra two clock cycles. The proposed CED architecture can therefore be utilized effectively in fault-tolerant cryptosystems.

关键词： Linear code Concurrent error detection(CED) Finite field multiplication

作者: Chiou-Yng Lee

作者单位: Department of Computer Information and Network Engineering Lunghwa University of Science and Technology, TAIWAN

会议类型: 国际会议

会议名称: International Conference on Computational Aspects of Social Networks(国际社会网络计算会议 CASoN 2010)

会议地点: 太原

会议语种:英文

页码: 111-115

在线出版日期: 2010-09-26（万方平台首次上网日期，不代表论文的发表时间）