Low Power State Machine Design on FPGAs

摘要：

This paper presents an approach to reduce the power consumption of FPGA based digital circuits at FSM design level. The approach is based on clock gating technique. By using control signals at FSM level, we have limited the clock switching and other signals transitions in the system, leading to reduced dynamic power consumption of the systems. Our results have shown up to 7％ reduction in dynamic power consumption.

关键词： Clock gating FPGA Low power FSM

作者: Adil Saleem Shoab A Khan

作者单位: Department of Computer EngineeringNUST, College of E&MERawalpindi, Pakistan Department of Computer Engineering NUST, College of E&ME Rawalpindi, Pakistan

会议类型: 国际会议

会议名称: 2010 3rd International Conference on Advanced Computer Theory and Engineering(2010年第三届先进计算机理论与工程国际会议 ICACTE 2010)

会议地点: 成都

会议语种:英文

页码: 1-4

在线出版日期: 2010-08-20（万方平台首次上网日期，不代表论文的发表时间）