FPGA-Based Embedded Speed Limit Enforcement System on Freeway
Speeding is recognized as a major contributing factor in traffic accidents on freeway. In order to reduce speed-related accidents, accurate real-time speed limit enforcement system is very critical to freeway. This paper presents an automatic speed limit enforcement system on freeway based on cameras and the Field Programmable Gate Array (FPGA) implementation to achieve this objective. Taking the advantage of the powerful parallel processing architecture of FPGA, this FPGA-based system can provide a real-time, low-cost, high-performance hardware platform for multi-channel video system to achieve real-time image processing. Once the speeding vehicle is detected, the system will immediately record the panoramic view of the vehicle passing and basic characteristics of the vehicle, shoot of the vehicle number plate, the vehicle speed, passing time, etc., and send this information to the monitoring center by the wireless modem through the serial interface and the GPRS network. The experiments indicated that the speed limit enforcement system can detect the vehicle speed accurately and provide the necessary proof for the police to enact punishment.
intelligent transportation speed limit enforcement system FPGA freeway P-tile threshold segmentation method
FU Jian-qun SHI Zhong-ke
College of Automation, Northwestern Polytechnical University, Xi’an 710072, China
国际会议
成都
英文
1-5
2010-08-20（万方平台首次上网日期，不代表论文的发表时间）