Efficient Hardware Architecture of SHA-512 Algorithm
Hash algorithm is always used as key primitives supporting information integrity and command authentication. In some cases, such as mobile platform, stringent limitations with respect to available power, physical circuit area, and cost are required. Therefore, special architecture and design methods for a compact hash hardware module are required. In this paper, a compact SHA-512 hardware architecture was proposed, which had low-area characteristics. Our SHA-512 hardware can compute 1024-bit data block using 1358 ALUTS on Stratix II FPGA. The highest operation frequency and throughput of the proposed architecture are 137 MHz and 121.8 Mbps.
SHA-512 Message compression Message Schedule Resource share
Chen Huafeng Zhuang Jianzhong
Zhejiang University of Media and Communications, Hangzhou 310018 China
国际会议
武汉
英文
787-790
2010-06-06（万方平台首次上网日期，不代表论文的发表时间）