Design and Optimization of Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock

摘要：

A low-power divide-by-4/5 unit of a prescaler is proposed. The power consumption and operating frequency of the extended true-single-phase-clock (ETSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the ETSPC-based divider are analyzed. Compared with the existing design, a 20％ reduction of power consumption is achieved. A divide-by-16/17 dual-modulus prescaler implemented with this divide-by-4/5 unit using a 0.18-um CMOS process is capable of operating up to 4.1 GHz with a low-power comsumpti-on. The prescaler is implemented in low-power high-resolution frequency dividers for wireless short distance application.

作者: Chao Guo Siheng Zhu Jun Hu Jing Diao Houjun Sun Xin Lv

作者单位: School of Information Science and Technology, Beijing Institute of Technology, 100081

会议类型: 国际会议

会议名称: 2010 International Conference on Microwave and Millimeter Wave Technology(2010国际微波与毫米波技术会议 ICMMT2010)

会议地点: 成都

会议语种:英文

页码: 636-638

在线出版日期: 2010-05-08（万方平台首次上网日期，不代表论文的发表时间）