A UWB Down Convert Circuit and Measurement

摘要：

This article presents a UWB receiver, which is made by the chips designed by our group in SMIC0.18μm process, This receiver was verified by the measurement, With the help of FPGA it can synthesis 2.8G~3.98CHz LO frequency by changing the PLL and reference frequency, with reference frequency 21MHz,division ratio 1/160,it can be locked at 3.36GHz with the phase noise of -83dBc/Hz,the internal Digital VGA could be digitally controlled by FPGA with 30dB tuning range. Though Chip scope verification, This receiver can demodulate 500MHz Bandwidth signal without error bit rate by connected the receiver and transmitter with RF line return loss of 40dB,the power consumption of this receiver is 60mW.

关键词： Digital-assisted RF UWB VGA

作者: Bo Han Mengmeng Liu Ning Ge

作者单位: State Key Laboratory on Microwave and Digital Communications Department of Microelectronics, Electronic Engineering Tsinghua University Beijing, China

会议类型: 国际会议

会议名称: 2010 International Conference on Microwave and Millimeter Wave Technology(2010国际微波与毫米波技术会议 ICMMT2010)

会议地点: 成都

会议语种:英文

页码: 1472-1475

在线出版日期: 2010-05-08（万方平台首次上网日期，不代表论文的发表时间）