High-Speed Modular Multipliers Based on a New Binary Signed-Digit Adder Tree Structure
In this paper, we present multipliers using a modified binary tree of the modulo m signed-digit (SD) number residue adders where m=2n-1,2n,2n+1. New additions rules are used for generating the intermediate sum and carry with a binary number representation. The sums and carries are directly inputted into the next stage of adders, so that the modulo m multiplier using binary modulo m adder tree proposed in 13 can be improved. Moreover residue multipliers using the SD residue adders are also designed with inputs/outputs in binary number representation. The design and simulation results of the proposed residue arithmetic circuits show that high speed arithmetic circuits can be obtained.
SD (signed-Digit) number representation residue number system SD modulo addition SD modulo multiplication
Mingda Zhang Shugang Wei
Department of Computer Science and Technology Gunma University Kiryu-shi, Gunma, Japan 376-8515
国际会议
香港
英文
615-619
2010-08-12（万方平台首次上网日期，不代表论文的发表时间）