Integrating Design-for-Test Techniques for On-Line Test of System-on-Chip
A new design-for-test (DFT) approach to perform online test of System-on-Chip (SoC) is proposed to minimize the hardware cost and test time. The basic idea of the approach consists in the reuse of the IIPs embedded into the system to face manufacturing and production testing issues. These structures are activated whenever an allowed time slot is identified in order to not impact the functionalities of the SoC. A real case of study results indicate that the method is feasible and it performs well for fault coverage.
SoC DFT BIST on-line test I-Ips
Wang Ying Fan Xinnan
School of Information Engineering,Beijing Geely University,Beijing,102202,China
国际会议
厦门
英文
31-34
2010-05-22（万方平台首次上网日期，不代表论文的发表时间）