会议专题

Hardware Realization of Concise Evolutionary Algorithm on FPEA

Traditional evolutionary algorithms require a lot of memory and processing power on embedded logic projects. Representing populations of candidate solutions through vectors of probabilities rather than sets of bit strings saves memory and processing. The concise evolutionary algorithm (CEA) is a probability vector based evolutionary algorithm. The article presents an FPEA realization of the standard concise evolutionary algorithm with a few changes to improve search power. A data flow and a block diagram design are shown and described in the paper. Results demonstrate the requirements (logical blocks) needed for realization, the architecture processing speed and the solving power of the CEA for Evolutionary Hardware.

Evolutionary Algorithm Evolutionary Hardware FPEA

Shengli Yan Yue Chen Qingmin Pu

Dept. of Electronic Information Engineering Zhongshan Polytechnic Zhongshan, Guangzho Province 528404, China

国际会议

2009 IEEE 10th International Conference on Computer-Aided Industrial Design & Conceptual Design(2009 IEEE 第十届国际计算机辅助工业设计与概念设计学术会议 CAID&CD2009)

温州

英文

2370-2373

2009-11-26(万方平台首次上网日期,不代表论文的发表时间)