High Voltage SJ-pLDMOS with Variation Lateral Doping Drift Layer

摘要：

This paper reports a novel Super Junction pLDMOS (SJ-pLDMOS) with charge-balanced SJ region at the surface of Variation Lateral Doping (VLD) drift region. SJ region provides a low on-resistance path in the ON-state and keeps charge balance approximately when the doping concentration of p pillars is slightly higher than that of the n pillars during the OFF-state. A significant reduction of the specific on-resistance for a given Breakdown Voltage (BV) can be achieved by using a high aspect ratio of the SJ pillars. Simulation results show that the SJ-pLDMOS with Ld of 35μm exhibits BV of 582V and Ron,SP of 210mΩ.cm2, yielding to a power Figure Of Merit (FOM) of 1.6 MW/cm2. These excellent device performances make the proposed SJ-pLDMOS a promising candidate for level shift circuit.

作者: Bo Luo Ming Qiao Yongchun Wang Mingliang Kou Jun Ye Bo Zhang Zhaoji Li

作者单位: State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

会议类型: 国际会议

会议名称: 2010 International Conference on Communications,Circuits and Systems(2010年通信、电路与系统国际会议)

会议地点: 成都

会议语种:英文

页码: 503-506

在线出版日期: 2010-06-28（万方平台首次上网日期，不代表论文的发表时间）