A Novel Hardware Method to Implement a Routing Algorithm onto Network on Chip

摘要：

Recently, a Network on Chip (NoC) has attracted much attention for its smart structure and high performance. However, NoC routing algorithms significantly influences the performance and design cost. In this paper, a new hardware method to implement a routing algorithm is proposed. The proposed method is used to replace the general destinationtag method for router design. We simulate and evaluate the router and NoC with proposed method in terms of circuit resource, latency and throughput. The results indicate that the NoC architecture with proposed method is effective in reducing circuit resource, latency and increasing throughput.

作者: Yiping Dong Hua Zhang Zhen Lin Takahiro Watanabe

作者单位: Graduate School of Information, Production and Systems, Waseda University, 2-7 Hibikino, Wakamatsu-ku, Kitakyushu, Fukuoka, Japan

会议类型: 国际会议

会议名称: 2010 International Conference on Communications,Circuits and Systems(2010年通信、电路与系统国际会议)

会议地点: 成都

会议语种:英文

页码: 852-856

在线出版日期: 2010-06-28（万方平台首次上网日期，不代表论文的发表时间）