A Parasitic Extraction Method of VLSI Interconnects for Pre-Route Timing Analysis

摘要：

For faster timing closure, a parasitic extraction method is developed for the pre-route VLSI design. This method generates virtual route and estimates congestion using the placement information of standard cells, and then extract the interconnect parasitics with the pattern-library method. The techniques of generating parasitic RC tree according to the improved FLUTE algorithm, and capacitance extraction of route segment considering congestion are presented. Experiments are carried out on industrial design cases, whose results show that the proposed method has high computational speed and comparable accuracy as commercial tool.

作者: Weibing Gong Wenjian Yu Yongqiang Lü Qiming Tang Qiang Zhou Yici Cai

作者单位: School of Mathematics and Statistics, Lanzhou University, Lanzhou, China Department of Computer Scie Department of Computer Science and Technology, Tsinghua University, Beijing, China

会议类型: 国际会议

会议名称: 2010 International Conference on Communications,Circuits and Systems(2010年通信、电路与系统国际会议)

会议地点: 成都

会议语种:英文

页码: 871-875

在线出版日期: 2010-06-28（万方平台首次上网日期，不代表论文的发表时间）