On Handling Fixed Blocks in Incremental Fixed-outline Floorplanning
Unlike classical floorplanning that usually only handles block packing to minimize silicon area, modern VLSI floorplanning typically needs to pack blocks within a fixed die(outline) with various user defined constraints. Many algorithms of floorplanning now are with fixed-outline constraint, and these algorithms handle this constraint in the process of stochastic iterative optimization. But the process not only costs too much run time but also is really hard to converge when additional constrains are included. To meet the incremental design requirements, an algorithm to handle fixedblocks constraints based on given fixed-outline packing with post process is proposed in this paper. By adjusting critical path iteratively in graph of TCG, the violated fixed-outline constraints can be fixed. At the same time, virtual nodes are added into TCG for the constrained blocks with fixed positions so that both fixed-outline constraints and fixed-blocks constraints can be satisfied during the incremental process. Experimental results on MCNC benchmarks show that our algorithm can fix all the violations effectively that for ami49 with 49 blocks, it only takes less than 0.3s to handle the fixedoutline constraints. The degradation on area and wirelength are controlled to about 1.3％ and 19.5％ respectively.
Zhigang He Yuchun Ma Ning Xu Yu Wang Xianlong Hong
School of Computer Science and Technology, WuHan University of Technology, WuHan, China Department o Tsinghua National Laboratory for Information Science and Technology Department of Computer Science a School of Computer Science and Technology, WuHan University of Technology, WuHan, China Tsinghua National Laboratory for Information Science and Technology Department of Electronic Enginee Tsinghua National Laboratory for Information Science and Technology
国际会议
2010 International Conference on Communications,Circuits and Systems(2010年通信、电路与系统国际会议)
成都
英文
876-880
2010-06-28（万方平台首次上网日期，不代表论文的发表时间）