A Run-Time RTL Debugging Methodology for FPGA-based Co-Simulation

摘要：

Logic simulation provides SoC verification with full controllability and observability, but it suffers from very slow simulation speed for complex design. Using hardware emulation such as FPGA can have higher simulation speed. However, it is very hard to debug due to its poor visibility. FPGA-based cosimulation seems to draw a balance, but Design Under Test (DUT) still resides in FPGA and remains hard for debugging. So a run-time RTL debugging methodology for FPGA-assisted verification system is presented. This method provides internal nodes probing on an event-driven cosimulation platform and achieves full observability for DUT. The debugging tools are embedded in HDL simulator using Verilog VPI callback, so signals of testbench and internal nodes of DUT can be observed in a single waveform and updated as simulation runs, making debugging more efficient. The proposed debugging method connects internal nodes directly to a PCI-extended bus, instead of inserting extra scan-chain logic, so the overhead for area is reduced. Our experiment shows that, compared with a similar method in 13, the area overhead for debug logic is reduced by 30～50％ and compile time is shortened by 40～70％.

作者: X. Cheng A.W. Ruan Y.B. Liao P. Li H.C. Huang

作者单位: State key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science & Technology of China, Chengdu 610054, P.R.China

会议类型: 国际会议

会议名称: 2010 International Conference on Communications,Circuits and Systems(2010年通信、电路与系统国际会议)

会议地点: 成都

会议语种:英文

页码: 891-895

在线出版日期: 2010-06-28（万方平台首次上网日期，不代表论文的发表时间）