A Non-iterative Effective Capacitance Model for CMOS Gate Delay Computing

摘要：

In Static Timing Analysis, the conventional methods usually use an iterative method to ensure the accuracy of the effective capacitance Ceff , which is usually used to compute the delay of gate with interconnect load and to capture the output signal shape of the real gate response. In this paper, a polynomial approximation method is used to make the nonlinear Ceff equation be solved without iterative method. Compared to the conventional methods, the proposed method has the merit of improving the efficiency for Ceff calculation. Meanwhile, experimental results show that the proposed method is in agreement with the Spice simulation.

作者: Minglu Jiang Qiang Li Zhangcai Huang Yasuaki Inoue

作者单位: Graduate School of Information, Production and Systems, Waseda University, Kitakyushu, 808-0135 Japa Fukuoka Industry, Science and Technology Foundation, Fukuoka, 814-0001 Japan

会议类型: 国际会议

会议名称: 2010 International Conference on Communications,Circuits and Systems(2010年通信、电路与系统国际会议)

会议地点: 成都

会议语种:英文

页码: 896-900

在线出版日期: 2010-06-28（万方平台首次上网日期，不代表论文的发表时间）