The Self-biased Based PLL with Fast Lock Circuit

摘要：

This paper presents a design of a self-biased based PLL with fast lock circuit, which achieves process technology independence, fixed damping factor, fixed ratio bandwidth related operating frequency, and fast lock time. The lock time of the PLL could be adjusted by demand. The input reference frequency is 125MHz and the PLL generates fixed output frequency of 1250MHz.

作者: Wei xueming Li ping

作者单位: State key laboratory of electronic thin films and integrated devices, University of Electronic Science & Technology of China, Chengdu, 610054, P.R. China

会议类型: 国际会议

会议名称: 2010 International Conference on Communications,Circuits and Systems(2010年通信、电路与系统国际会议)

会议地点: 成都

会议语种:英文

页码: 901-904

在线出版日期: 2010-06-28（万方平台首次上网日期，不代表论文的发表时间）