A Pipelining Hardware Implementation of H.264 Based on FPGA

摘要：

A two-dimensional discrete cosine transform (DCT) module for the JPEG image compression system is designed. Considering the compromise of resource and speed in the FPGA chip, two same ID-DCT module are reused to complete the FPGA design of 2D-DCT. The pipelining levels in the module are also analyzed and optimized. Simulation and test results for the whole system based on EP1C6Q240C8 show that it can perform the integer DCT of 4×4 block in twelve clock cycles and 10％ resource consumption rate. It provides a exploring attempt and a positive reference on the JPEG encoder system IP core design and their FPGA implementation.

关键词： JPEG Discrete Cosine Transform Pipelining level FPGA

作者: Sun Song Qi Haibing

作者单位: School of Electric and Electronic Information Engineering, Huangshi Institute of Technology, Huangshi 435003, China

会议类型: 国际会议

会议名称: 2010 International Conference on Intelligent Computation Technology and Automation(2010 智能计算技术与自动化国际会议 ICICTA 2010)

会议地点: 长沙

会议语种:英文

页码: 299-302

在线出版日期: 2010-05-11（万方平台首次上网日期，不代表论文的发表时间）