A Sigma-Delta Fractional-N Frequency Synthesizer based on ADPLL

摘要：

In this paper, we propose a fractionaI-N frequency synthesizer based on All Digital Phase Locked Loop (ADPLL). We use phase-frequency detector as PD, up/down counter as LF, P-Divider counter as DCO, and the dual-modulus N/N+1 divider is controlled by the output of the sigmadelta modulation to achieve the goal of spur reduction. The Sigma Delta Modulator (SDM) have noise-shaping characteristic though SDM will introduce inevitable quantization noise. We discuss the phase noise caused by the quantization noise brought by the Sigma-Delta noise-shaping technique.

关键词： Frequency Synthesizer ADPLL Fractional-N Sigma-Delta Noise-Shaping

作者: Wei Sun Hexiang Wen Lizhong Gao

作者单位: School of Information Science and Engineering Southeast University Nanjing, China

会议类型: 国际会议

会议名称: 2010 International Conference on Intelligent Computation Technology and Automation(2010 智能计算技术与自动化国际会议 ICICTA 2010)

会议地点: 长沙

会议语种:英文

页码: 340-342

在线出版日期: 2010-05-11（万方平台首次上网日期，不代表论文的发表时间）