Threshold Voltage Increasing Induced By Poly Silicon Gate Counter Pre-doping in NMOSFET
Gate poly-silicon (poly Si) pre-doping for both NMOS and PMOS is widely used in current CMOS technology to alleviate the poly Si depletion effect (PDE). Unlike the general poly Si pre-doping way, where NMOS and PMOS poly Si are separately doped with independent photolithography, the NMOS poly Si counter pre-doping (PMOS poly Si is P-type blankly doped without photolithography first, and NMOS is Ntype doped with high dose to counter the blankly implanted P-type dopant) feasibility is fully studied in the paper. NMOS threshold voltage (Vth) shows ～20mV anomalous increase when poly Si counter predoping is adopted. It is revealed that the Vth increase is originated from gate stack flat band voltage shift in the positive direction. Considering the lower body effect factor (Gamma) value of poly Si counter predoping device, it is speculated that NMOS high phosphorous (P) counter pre-doping dose (up to 4E15/cm2) leads to P penetration through the gate oxide and causes negative charge in the gate oxide simultaneously. However, gate oxide GOI and NMOS HCI features all show that the poly Si counter pre-doping does not deteriorate gate oxide reliability. This result is also supported by device performance data as no performance difference is seen between devices with and without poly Si counter pre-doping. Moreover, 16M SRAM characteristics also exhibit that NMOS poly counter pre-doping does not degrade SRAM Vccmin performance either.
Jinhua Liu Hokmin_Ho Jay Ning IC Chen Allan Zhou Kevin Zheng Jimmy Wu Howard Gan Shuaigong Chen Huachun Guo Guiming Wang Jianhua Ju
Logic Technology Development Center, SMIC (BJ) Beijing 100176, PRC
国际会议
China Semiconductor Technology International Conference 2010(中国国际半导体技术大会 CSTIC)
上海
英文
33-38
2010-03-18（万方平台首次上网日期，不代表论文的发表时间）