Wafer-Area-Saving Test Structures and Measurement Method for The Characterization of Interconnect Resistance and Capacitance in Nanometer Technologies

摘要：

Interconnect parasitic parameters are the dominant source for delay and noise in modern integrated circuits. Aggressive technology scaling has led to much higher resistance and larger coupling capacitance on interconnect. To predict the impact of interconnect to the circuit performance by accurately extracting electrical parameters of interconnect for circuit simulation, a novel test structure and an effective measurement method, which consumes less wafer area and hence results in lower production cost, are proposed in this paper. The method could be easily implemented for device characterization for DFM (design-for-manufacturing) applications.

作者: Xiaojing Qin Lele Jiang Yuhua Cheng

作者单位: Shanghai Research Institute of Microelectronics (SHRIME), Peking University, Shanghai 201203, China Shanghai Research Institute of Microelectronics (SHRIME), Peking University, Shanghai 201203, China Shanghai Research Institute of Microelectronics (SHRIME), Peking University, Shanghai 201203, China

会议类型: 国际会议

会议名称: China Semiconductor Technology International Conference 2010(中国国际半导体技术大会 CSTIC)

会议地点: 上海

会议语种:英文

页码: 163-168

在线出版日期: 2010-03-18（万方平台首次上网日期，不代表论文的发表时间）