Advanced In-line Monitoring BrightField Inspection Tool for E-test Correlation and Yield Analysis on 45nm Test Chips
With advanced design rules, yield learning challenges have scaled up. Identifying and analyzing yield killer defects are one of the major part of the issue. In this work, an advanced in-line inspection platform - 2810 DUV Broadband Brightfield Inspection tool and Test chips are used to identify systematic as well as random defects causing yield drop, and monitor key DOI (Defects-of-Interest) for accelerated defect-based yield learning at the 45nm technology node. 2810 DUV Broadband illumination, in-line defect organizer iDO & RICO Review inspector cycle optimization of eDR SEM review tool are key features employed during inspection recipe optimization. The test chips contained diverse pattern lay-outs which provide platform for characterization of yield limiting factors. Using this methodology, E-test - In-line defect detection correlation was matched to target benchmark capture rate values for FEOL and BEOL at Samsung S-1, a leading 300mm fab. Learnings derived from this study have enabled faster yield ramp-up on production devices.
YoungHun Kwon Grant Shoji Keebum Jung HyeongJu Choi JongPil Kim Vijay Ramani Satya Kurada HakYu Yoon HoSeong Kang KiHo Kim MinHo Kim YoungSun Oh JunWoo Lee Vikram Gunda HeungSoo Choi
Samsung Electronics, Kiehung, Gyeonggi-Do 446-711, South Korea KLA-Tencor Corp, Milpitas, California 95035, U.S.A.
国际会议
China Semiconductor Technology International Conference 2010(中国国际半导体技术大会 CSTIC)
上海
英文
209-214
2010-03-18（万方平台首次上网日期，不代表论文的发表时间）