Improvement of Characteristic Ramped Voltage Breakdown in Multi-level Cu/SiOC Low k Integration
As the interconnect RC delay becomes a dominant factor in determining the overall circuit performance, the advantages of Cu and low k materials become more remarkable. The introduction of new materials is driving significant research of the impact of these materials on the reliability. Active investigation is focus on the impact of back end of line (BEOL) processing on Cu/low k reliability. Until now, the investigation mainly focuses on the EM and SM, etc. In this paper, inter layer dielectric (ILD) characteristic ramped voltage breakdown (VBD) of multiplayer Cu/SiOC interconnect was investigated. It was found the breakdown performance is highly process-related. Some process/integration changes have significant influence on VBD performance, such as some specific treatment to Cu surface, application of capping layer, and modified deposition process of etch stop layer (ESL), etc.
Y. W. Chen Johnston Zou Steven Chen E. Bei Jimmy Wang
Semiconductor Manufacturing International Corporation 18 Zhangjiang Rd., Pudong New Area, Shanghai 201203, P. R. China
国际会议
China Semiconductor Technology International Conference 2010(中国国际半导体技术大会 CSTIC)
上海
英文
345-349
2010-03-18（万方平台首次上网日期，不代表论文的发表时间）