Achieving Fast Yield Improvement by Defect to Bit Failure Overlay Method

摘要：

In this paper, we present a new proven methodology, which identifies the killer defects and marginal designs by overlaying the electrical failure signatures and addresses from wafer sort to the inline defect inspection results. Not only have this new approach helped identifying killer defects that are difficult to PFA, it also benefits inspection recipe tuning and finding the root causes of different defects. This approach has been successfully implemented in 40/45nm products, and shortened the yield learn cycle significantly.

作者: Cinti Chen Joe Zhao Gang Qian Jenny Fan Xiao-Yu Li

作者单位: Quality and New Product Introduction Group, Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124, USA Quality and New Product Introduction Group, Xilinx, Inc. 2100 Logic Drive, San Jose,CA 95124, USA

会议类型: 国际会议

会议名称: China Semiconductor Technology International Conference 2010(中国国际半导体技术大会 CSTIC)

会议地点: 上海

会议语种:英文

页码: 401-406

在线出版日期: 2010-03-18（万方平台首次上网日期，不代表论文的发表时间）