Lithographic Significance of Wafer Back Surface Nanotopography
Wafer topography plays a critical role in the performance of lithography at smaller nodes. The contribution of low to medium spatial frequency components of wafer topography to overlay error is currently a topic of interest within the lithography community, especially as double patterning techniques have reduced overlay error budgets by a factor of two. Nanotopography, comprised of the higher spatial frequency components of wafer topography can contribute to non-correctable errors (NCE) for the scanner. In this paper we use finite element analysis to investigate the transfer of back-surface nanotopography to the front surface as the wafer is chucked either on a pin chuck or a flat vacuum chuck. The results are found to be lithographically significant, suggesting that fabs may benefit from measuring back-surface nanotopography, and developing appropriate specs for incoming wafers.
Sathish Veeraraghavan Jaydeep K. Sinha
Wafer Inspection Group, KLA-Tencor Corp., CA 95035, USA
国际会议
China Semiconductor Technology International Conference 2010(中国国际半导体技术大会 CSTIC)
上海
英文
509-514
2010-03-18（万方平台首次上网日期，不代表论文的发表时间）