CMP Process Technology in TSV Application
Through-silicon via (TSV), an emerging technology for 3D IC manufacturing, involves fabrication of vertical vias through the wafers. The two methods commonly used involve via-first and via-last process flows. While the via-last approach appears to be relatively simple with minimum impact to circuit layout, the viafirst scheme may ultimately offer more benefits by enabling a higher density of I/Os. This paper describes the rapid progress made in the process integration of CMP for TSV, to offer unique advantages especially in the via-first approach where planarity is critical. In addition, with backside polishing after wafer thinning, the CMP process ensures a smooth surface finish for bonding and provide extra process knobs to correct the non-uniformity in via depths caused by preceding via etch and silicon grinding processes.
Yuchun Wang Max Gage Sherry Xia Wen-Chiang Tu Lakshmanan Karuppiah
CMP Division, Silicon Systems Group, Applied Materials Sunnyvale, CA 94085, USA
国际会议
China Semiconductor Technology International Conference 2010(中国国际半导体技术大会 CSTIC)
上海
英文
533-538
2010-03-18（万方平台首次上网日期，不代表论文的发表时间）