Packaging Challenges on Shrink Chip Technology
As technology grows, semiconductor industry evolved towards tinier & thinner packages to meet market demand. To create competitiveness, chip size shrinkage at front-end wafer fabrication is essential for newer packages technology. With the tireless effort from front-end fab, die size & thickness are reduced up to 30％. There are changes on wire bond pad as well, pad opening is reduced & pad metallization is changed to NiPPdAu with barrier metal underneath. This paper will discuss in details mainly on die bonding & wire bonding challenges for shrink chip technology. Critical defects such as vertical crack die, die surface contamination & passivation crack were observed during process development stage. Several efforts were made to address them accordingly. Finally this paper will share on new failure mechanism observed during ramp up, evaluations for risk assessment & future improvement ideas to overcome mass production obstacles.
YANG Xiao SOH Yuen Chun WU Huiliang
Infineon Technologies (Wuxi) Co., Ltd
国际会议
China Semiconductor Technology International Conference 2010(中国国际半导体技术大会 CSTIC)
上海
英文
915-921
2010-03-18（万方平台首次上网日期，不代表论文的发表时间）