An Overview of Data Bandwidth Hierarchy for an Embedded Stream Processor
The overall speed of computation is determined not just by the speed of the processor, but also by the ability of the memory system to feed data to it. Imagine is a novel image processor which is constructed by a research group of Stanford University. A brand new data bandwidth hierarchy of this processor is introduced in this article. This new data bandwidth hierarchy is constructed by local register file(LRF), stream register file(SRF) and main memory. LRF is used by the ALU clusters. SRF looks like cache in traditional processor. But SRF is a specific unit in stream processor. SRF is used as a stream load/store unit in stream processor. Using this kind of data bandwidth hierarchy the image processing speed is improved greatly.
data bandwidth hierarchy Imagine stream processor embedded image processor computer architecture
Duan zongtao Zhang yanni Duan zongyuan
Information College, Changan University, xian Shaanxi 710064, China Xian Metrology & Measurement Technique Institute, xian Shaanxi 710068, China Xian Objective Software Company, xian Shaanxi 710068, China
国际会议
重庆
英文
34-36
2009-12-25（万方平台首次上网日期，不代表论文的发表时间）