Design and Realization of Image Acquisition IP Core Based on Avalon Bus

摘要：

The present study puts forward a new IP core design for real-time, high-speed image acquisition, based on Avalon bus. The proposed design can be described as follows. First, according to the top-down design philosophy, the IP core was functionally partitioned and hierarchically divided. Second, the IP core was driven and encapsulated under the HAL API. Third, the customized peripheral was added into Nios Ⅱ system. The following experiment validated the low-power, high real-time of this IP core. Thus the customized image acquisition IP core based on Avalon bus was designed, realized and validated. Since IP core is configurable and can be well transplanted, it can be easily applied to embedded image acquisition system. And the IP core designed above has good portability and universal property.

关键词： FPGA SOPC Avalon bus image acquisition IP core

作者: Lushen Wu Wenkai Ding

作者单位: School of Mechanical and Electronical Engineering, Nanchang University, Nanchang, China Electronic Information Engineering Department, Nanchang University, Nanchang, China

会议类型: 国际会议

会议名称: 2009 International Workshop on Information Security and Application(2009 信息安全与应用国际研讨会)

会议地点: 青岛

会议语种:英文

页码: 31-34

在线出版日期: 2009-11-21（万方平台首次上网日期，不代表论文的发表时间）