A Study of Optimized Subtask Scheduling Order on Reconfigurable Architecture
The scheduling of subtask-execution orders is a performance bottleneck for reconfigurable computing systems targeting regular and high-intensive applications. This paper studies this problem based on DReAC-2 reconfigurable computing system, including a Nios Ⅱ processor, an 8×8 processing nodes array and some memory units. An optimized method for scheduling subtask execution orders is proposed to accelerate the execution speed of applications by reducing the configuration instruction loading. Some typical applications are mapped on DReAC-2 with different subtask-execution orders to figure out the advantage of this method. All tests are performed with DReAC-2 hardware prototype which is based on the Altera STRATIX Ⅱ EP2S180 development board. The results show that the most optimal subtask execution orders for these applications may result in 1.5 49X faster than the original ones.
reconfigurable computing scheduling subtask-execution orders method for optimized orders configuration-instruction loading task decompounded
Yukun Song Wei Ni Duoli Zhang Xiaolei Wang
Institute of VLSI Design, Hefei University Technology Hefei, China
国际会议
2009 International Workshop on Information Security and Application(2009 信息安全与应用国际研讨会)
青岛
英文
477-480
2009-11-21（万方平台首次上网日期，不代表论文的发表时间）