Implementation of Haar Transform with PDDA Architecture for Flexible Scales

摘要：

In this paper,a novel approach to the flexible scales of Haar wavelet transform in FPGAs is proposed, which could be achieved by only a single Parallel Dynamic Distributed Arithmetic(PDDA)FIR architecture with some pipelining registers.In addition, floating-point system is adopted to provide higher resolution over a large dynamic range.Furthermore,the scheme is mapped into a Xilinx Virtex5 FPGA chip.The synthesis results demonstrate it performs faster and consumes less resource under the same precision compared with conventional methods.

关键词： wavelet DA real-time signal processing FPGA

作者: Zhu Bo Shi Rong Wan Qun

作者单位: National Information Control Laboratory Chengdu,China National Information Control Laboratory Chengdu, China Electrical Engineering Department University of Electronic Science and Technology of China Chengdu,

会议类型: 国际会议

会议名称: 2009 Second International Conference on Intelligent Computation Technology and Automation(2009 第二届IEEE智能计算与自动化国际会议 ICICTA 2009)

会议地点: 长沙

会议语种:英文

页码: 617-620

在线出版日期: 2009-10-10（万方平台首次上网日期，不代表论文的发表时间）