An Embedded 14-Bit 800MS/s DAC for Direct Digital Frequency Synthesizer in 0.18-μm CMOS

摘要：

An embedded 14-bit 1-GS/s digital-to-analog converter for Direct Digital Frequency Synthesizer (DDFS) application is presented. The DAC is implemented using a segmented currentsteering architecture, with the top 6bits and the remaining 8 bits. The output stage of dual return-to-zero scheme is used to enhance the dynamic performance of spurious-free dynamic range (SFDR). The DAC core is fabricated in a 1P6M 0.18 μm standard CMOS technology occupies a die area of only 1.6 × 1.5 mm2. The measured differential nonlinearity lies between -0.8 LSB and 0.3LSB, integral nonlinearity lies between -1.5LSB and 1LSB. And the SFDR is 76.47 dB for 80 MHz output at 0.8GHz sampling clock rate.

关键词： DAC Current steering DDFS Dual return-to-zero

作者: Shuqin Wan Zhenhai Chen Zongguang Yu

作者单位: Dept. of Information Technology Southern Yangtze University Wuxi, China Songren Huang, Huicai Ji China Electronic Technology Group Corporation No.58 Research Institute Wuxi

会议类型: 国际会议

会议名称: 2009 International Conference on Applied Superconductivity and Electromagnetic Devices(应用超导与电磁装置技术国际会议 ASEME 2009)

会议地点: 成都

会议语种:英文

页码: 97-100

在线出版日期: 2009-09-25（万方平台首次上网日期，不代表论文的发表时间）