Experiment and Simulation of Transistor Level Fault Model of IDDT Test
Fault and fault model is the fundament of IC diagnosis. Fault model based on IDDT and its test is the hot issue of modern IC fault diagnosis at present. Open and short fault models of inverter, NAND gate, and SRAM of CMOS technology were built in this paper. In the experiments, we selected the deep sub-micron of 0.18 μm CMOS technology to simulate with HSPICE. The simulations of IDDT waveforms and FFT transform waveforms of different fault models were made and the results were indicated that the IDDT test method can detect the open and short fault of CMOS devices effectively.
IDDT COMS technology fault mode HSPICE
Shuyan Jiang Yongle Xie Dajin Yu Gang Luo
School of Automation Engineering University of Electronic Science and Technology of China Chengdu, C Mechanical Engineering Department Chengdu Electromechanical College Chengdu, China
国际会议
成都
英文
133-137
2009-09-25（万方平台首次上网日期，不代表论文的发表时间）