A New Design of HDB3 Encoder and Decoder Bsed on FPGA

摘要：

A new design of HDB3 encoder / decoder based on FPGA is proposed to deal with the high complexity and long output delay of the encoder and no error correction function of the decoder which have been implemented so far. The encoder has the function of converting a NRZ code sequence to a HDB3 sequence and the decoder, vice versa. Meanwhile the decoder can correct the errors in the received HDB3 sequence according to a certain rule. Synthesis reports show that the encoder and decoder are both simple–structured; Simulation results show that the encoder has a shorter output delay and the decoder has a better function of error detecting and correcting which greatly improves the reliability of the system.

关键词： HDB3 encoder decoder Verilog HDL FPGA

作者: Yang Zhang Xiumin Wang Yuduo Wang

作者单位: College of Information Engineering China Jiliang University Hangzhou,China School of Optoelectronic Information & Telecommunication Engineering Beijing Informaton Science&Tech

会议类型: 国际会议

会议名称: 2009 Ninth International Conference on Hybrid Intelligent Systems(第九届混合智能系统国际会议 HIS 2009)

会议地点: 沈阳

会议语种:英文

页码: 1-4

在线出版日期: 2009-08-12（万方平台首次上网日期，不代表论文的发表时间）