Wavelet Neural Networks Based Performance Estimation for Power Gating Domino Circuits

摘要：

A system for estimating the leakage power, the active power and the delay of the domino OR gates with the sleep transistor based on wavelet neural networks in 45 nm technology is proposed. By studying the impact of the power gating technique (PGT) on the power and delay characteristics, the proposed model could estimate the nonlinear changing of the active power, the leakage power and the delay of the different inputs dynamic OR gates with fast speed convergence and high precision. The trend of the estimating curve is discussed. At last, the comparison between the footer and the header sleep transistor technique is given.

作者: Jinhui Wang Wuchen Wu Na Gong Lei Zuo Xiaohong Peng Ligang Hou

作者单位: VLSI & System Lab,Beijing University of Technology,Beijing 100022,China College of Electronic and Info Engineering,Hebei University,Baoding,071002,China

会议类型: 国际会议

会议名称: 2009 IEEE International Conference on Information and Automation(2009年 IEEE信息与自动化国际学术会议)

会议地点: 珠海、澳门

会议语种:英文

页码: 435-438

在线出版日期: 2009-06-22（万方平台首次上网日期，不代表论文的发表时间）