Research on FPGA Based Evolvable Hardware Chips for Solving Super-High Dimensional Equations Group

摘要：

Solving a super-high dimensional equations group is widely used in science and engineering, but the slow solution speed is the biggest problem researchers face. Research on FPGA based evolvable hardware chips for solving the super-high dimensional equations group (SHDESC) is proposed in this paper. These chips can be implemented on a million-gate scale FPGA chip. The core architecture of SHDESC is a systolic array which consists of thousands of special arithmetic units and can execute many super-high dimensional matrix operations parallelly in short time as well as really achieve the purpose of high speed solution in hardware/software codesign. The experiments show that these chips can achieve high precision results in a short period of time to solve a super-high dimensional equations group.

关键词： Evolvable hardware super-high dimension equations group FPGA hardware/software Codesign systolic array

作者: Kangshun Li Zhaolu Guo Zhangxin Chen Baoshan Ge

作者单位: School of Information, South China Agricultural University,Guangzhou 510642,School of Information En School of Information Engineering, Jiangxi University of Science and Technology,Ganzhou 341000, Chin Department of Chemical and Petroleum Engineering, Schulich School of Engineering,University of Calga Institue of Automation,Chinese Academy of Sciences, Beijing 100190, China

会议类型: 国际会议

会议名称: The Second International Conference on High Performance Computing and Applications(第二届高性能计算及应用国际会议)

会议地点: 上海

会议语种:英文

页码: 58-68

在线出版日期: 2009-08-10（万方平台首次上网日期，不代表论文的发表时间）