Ultra High Throughput Implementations for MD5 Hash Algorithm on FPGA

摘要：

This paper first presents a new architecture of MD5, which achieved the theoretical upper bound on throughput in the iterative architecture. And then based on the general proposed architecture, this paper implemented other two different kinds of pipelined architectures which are based on the iterative technique and the loop unrolling technique respectively. The latter with 32-stage pipelining reached a throughput up to 32.035Gbps on an Altera Stratix II GX EP2SGX90FF FPGA, and the speedup achieved 194x over the Intel Pentium 4 3.0 processor. At least to the authors knowledge, this is the fastest published FPGA-based design at the time of writing. At last the proposed designs are compared with other published MD5 designs, the designs in this paper have obvious advantages both in speed and logic requirements.

关键词： Secure hash algorithm MD5 Filed Programmable Gate Array (FPGA) Pipelining Loop unrolling Speedup

作者: Yuliang Wang Qiuxia Zhao Liehui Jiang Yi Shao

作者单位: China National Digital Switching System Engineering and Technological R&D Center,450002, Zhengzhou, China National Digital Switching System Engineering and Technological R&D Center,450002,Zhengzhou, C

会议类型: 国际会议

会议名称: The Second International Conference on High Performance Computing and Applications(第二届高性能计算及应用国际会议)

会议地点: 上海

会议语种:英文

页码: 433-441

在线出版日期: 2009-08-10（万方平台首次上网日期，不代表论文的发表时间）